The use of ESD protection circuitry for protecting an integrated circuit (IC) device from damage caused by the discharge of static electricity and/or other transient pulses (e.g., load dump) through the device is well known. An ESD event, which may include any large voltage and/or current transient pulse, may not necessarily cause immediate (i.e., catastrophic) failure of the device, but may damage only a portion of the device and/or cause a latent defect that can significantly shorten the operating life or negatively impact the reliability of the device.
Protection from ESD is critical in order to prevent damage to the gate oxide associated with, for example, a large power transistor of the metal-oxide-semiconductor (MOS) type. It is common to incorporate ESD protection circuitry for large transistors that can protect the gate oxides from damage and withstand a high current (e.g., several amperes) as a result of an ESD event. However, conventional ESD protection schemes for power transistors, including the use of zener diodes and/or grounded-gate n-type metal-oxide-semiconductor (NMOS) transistors, are generally not adequate for high frequency applications, which may require operation, for example, in a radio frequency (RF) range. This is primarily due to the large capacitances associated with traditional ESD protection structures having relatively large geometries, wide metal interconnects, large contacts, etc. Moreover, the large geometries required by such conventional ESD protection structures undesirably decrease the number of integrated circuits that can be fabricated on a given semiconductor wafer, thereby increasing the cost of manufacturing the device. Additionally, conventional ESD protection circuits often demonstrate other undesirable characteristics, such as, for example, being prone to false triggering during large signal operation of the device being protected, high leakage current, high and/or uncontrollable snapback voltage, etc.
Conventional approaches to manufacturing ESD protection structures often involve the use of several additional masks or reticles and corresponding fabrication steps. However, any increase in the number of masks and/or processing steps undesirably translates to an increase in the overall cost of IC fabrication. Moreover, each additional fabrication step presents an opportunity for the introduction of impurities into the resulting device, thus negatively impacting the manufacturing yield as well.
Accordingly, it would be advantageous to have an ESD protection circuit capable of protecting an IC device from damage caused by an ESD event without significantly impacting the high frequency performance of the device. Moreover, it would be desirable for the ESD protection circuit to be sized such that circuit density, and thus manufacturing cost, is not significantly affected.